diff options
| author |   Ramesh Errabolu <Ramesh.Errabolu@amd.com> | 2022-05-26 11:51:08 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-06-08 11:40:12 -0400 |
| commit | 6fbfc3a23c98bdcda679161c4f4e31368008af8a (patch) | |
| tree | cadcb25282be56ed8d6596f8c9d773b9c0b1c2cc /drivers/gpu/drm/amd/amdkfd/Kconfig | |
| parent | drm/amd/display: Reduce frame size in the bouding box for DCN20 (diff) | |
| download | linux-dev-6fbfc3a23c98bdcda679161c4f4e31368008af8a.tar.xz linux-dev-6fbfc3a23c98bdcda679161c4f4e31368008af8a.zip | |
drm/amdkfd: Define config HSA_AMD_P2P to support peer-to-peer
Extend current kernel config requirements of amdgpu by adding config
HSA_AMD_P2P. Enabling HSA_AMD_P2P is REQUIRED to support peer-to-peer
communication between AMD GPU devices over PCIe bus
Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdkfd/Kconfig')
| -rw-r--r-- | drivers/gpu/drm/amd/amdkfd/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig index 8cc0a76ddf9f..93bd4eda0d94 100644 --- a/drivers/gpu/drm/amd/amdkfd/Kconfig +++ b/drivers/gpu/drm/amd/amdkfd/Kconfig @@ -25,3 +25,17 @@ config HSA_AMD_SVM preemptions and one based on page faults. To enable page fault based memory management on most GFXv9 GPUs, set the module parameter amdgpu.noretry=0. + +config HSA_AMD_P2P + bool "HSA kernel driver support for peer-to-peer for AMD GPU devices" + depends on HSA_AMD && PCI_P2PDMA && DMABUF_MOVE_NOTIFY + help + Enable peer-to-peer (P2P) communication between AMD GPUs over + the PCIe bus. This can improve performance of multi-GPU compute + applications and libraries by enabling GPUs to access data directly + in peer GPUs' memory without intermediate copies in system memory. + + This P2P feature is only enabled on compatible chipsets, and between + GPUs with large memory BARs that expose the entire VRAM in PCIe bus + address space within the physical address limits of the GPUs. + |