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| author |   Hawking Zhang <Hawking.Zhang@amd.com> | 2021-06-07 13:22:08 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-06-11 16:06:21 -0400 |
| commit | 3a07101b0405c6137babd5f50ca6bdf2696d91c9 (patch) | |
| tree | 52d57576401d9f5f0d838752139fd61db3455914 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | |
| parent | drm/amdgpu: cache psp runtime boot_cfg_bitmask in sw_int (diff) | |
| download | linux-dev-3a07101b0405c6137babd5f50ca6bdf2696d91c9.tar.xz linux-dev-3a07101b0405c6137babd5f50ca6bdf2696d91c9.zip | |
drm/amdgpu: disable DRAM memory training when GECC is enabled
GECC and G6 mem training are mutually exclusive
functionalities. VBIOS/PSP will set the flag
(BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) in
runtime database to indicate whether dram memory
training need to be disabled or not.
For Navi1x families, two stage mem training is always
enabled.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c')
0 files changed, 0 insertions, 0 deletions