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| author |   Wayne Lin <Wayne.Lin@amd.com> | 2021-03-10 23:40:01 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-07-20 16:04:11 -0400 |
| commit | 8a9899c95d1cd709d441960ca325c6c8184978bb (patch) | |
| tree | f49614baa55169ec3df6e9128758d0876dd74a5b /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h | |
| parent | drm/amd/pm: enable gfx ulv and gpo on smu_v13_0_7 (diff) | |
| download | linux-dev-8a9899c95d1cd709d441960ca325c6c8184978bb.tar.xz linux-dev-8a9899c95d1cd709d441960ca325c6c8184978bb.zip | |
drm/amd/display: Support vertical interrupt 0 for all dcn ASIC
[Why]
When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try
to register vertical interrupt 0 for specific task.
Currently, only dcn10 have defined relevant info for vertical interrupt
0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will
get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and
cause pointer errors.
[How]
Add support of vertical interrupt 0 for all dcn ASIC.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h')
0 files changed, 0 insertions, 0 deletions