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| author |   Roman Li <Roman.Li@amd.com> | 2020-09-29 11:21:58 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-10-05 15:15:56 -0400 |
| commit | 3a83e4e64bb1522ddac67ffc787d1c38291e1a65 (patch) | |
| tree | 907efd005ca3c474afd17acae74f53aec1a8836e /drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | |
| parent | drm/amdgpu: enable gfx clock gating and power gating for vangogh (diff) | |
| download | linux-dev-3a83e4e64bb1522ddac67ffc787d1c38291e1a65.tar.xz linux-dev-3a83e4e64bb1522ddac67ffc787d1c38291e1a65.zip | |
drm/amd/display: Add dcn3.01 support to DC (v2)
Update dc for vangogh support.
v2: fix compilation without DCN 301 set.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index efb909ef7a0f..270a8182682d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -42,6 +42,9 @@ #if defined(CONFIG_DRM_AMD_DC_DCN3_0) #include "dcn30/dcn30_clk_mgr.h" #endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) +#include "dcn301/vg_clk_mgr.h" +#endif int clk_mgr_helper_get_active_display_cnt( @@ -188,6 +191,12 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p break; #endif /* Family RV and NV*/ +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) + case FAMILY_VGH: + if (ASICREV_IS_VANGOGH(asic_id.hw_internal_rev)) + vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + break; +#endif default: ASSERT(0); /* Unknown Asic */ break; @@ -205,8 +214,18 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) case FAMILY_NV: if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { dcn3_clk_mgr_destroy(clk_mgr); - break; } + break; + +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) + case FAMILY_VGH: + if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev)) + vg_clk_mgr_destroy(clk_mgr); + break; +#endif + + default: + break; } #endif |