diff options
| author |   Evan Quan <evan.quan@amd.com> | 2020-09-30 14:20:38 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-10-27 12:01:16 -0400 |
| commit | a2475e624e2e80e65f371d44b712c93a144bfad9 (patch) | |
| tree | 1e360080afbb6136ae09cd741e4f2c4984090034 /drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c | |
| parent | drm/amd/pm: drop redundant display setting (diff) | |
| download | linux-dev-a2475e624e2e80e65f371d44b712c93a144bfad9.tar.xz linux-dev-a2475e624e2e80e65f371d44b712c93a144bfad9.zip | |
drm/amd/display: correct asic type check V2
Check chip family also to avoid wrong identification.
V2: use the correct macro without AMDGPU prefix
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c index 807dca8f7d7a..934e6423dc1a 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c @@ -100,7 +100,9 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ dce_clk_params.target_clock_frequency = 0; dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; - if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) + + if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && + ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = (dce_clk_params.pll_id == CLOCK_SOURCE_COMBO_DISPLAY_PLL0); @@ -176,7 +178,8 @@ int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr) dce_clk_params.target_clock_frequency = 0; dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; - if (!ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev)) + if (!((clk_mgr->base.ctx->asic_id.chip_family == FAMILY_AI) && + ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev))) dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = (dce_clk_params.pll_id == CLOCK_SOURCE_COMBO_DISPLAY_PLL0); |