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authorCharlene Liu <charlene.liu@amd.com>2019-06-27 18:16:21 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-18 14:27:25 -0500
commit925f566cb7aedbcf26005035cf894ec824e8ca2f (patch)
tree06f5ac58c76e29af2bfce31f2adbf3787ae7bbda /drivers/gpu/drm/amd/display/dc/core/dc.c
parentdrm/amd/display: allocate 4 ddc engines for RV2 (diff)
downloadlinux-dev-925f566cb7aedbcf26005035cf894ec824e8ca2f.tar.xz
linux-dev-925f566cb7aedbcf26005035cf894ec824e8ca2f.zip
drm/amd/display: add set and get clock for testing purposes
add dc_set_clock add dc_get_clock this is for testing and diagnostics to get/set DPPCLK and DISPCLK. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a8516deb5ac3..c86c86c07fd9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2431,3 +2431,14 @@ void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx
info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
}
+enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
+{
+ if (dc->hwss.set_clock)
+ return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
+ return DC_ERROR_UNEXPECTED;
+}
+void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
+{
+ if (dc->hwss.get_clock)
+ dc->hwss.get_clock(dc, clock_type, clock_cfg);
+}