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authorMichael Strauss <michael.strauss@amd.com>2022-07-25 16:24:42 -0400
committerAlex Deucher <alexander.deucher@amd.com>2022-09-29 09:41:46 -0400
commite844cc250f33d207077d0af9337484d6c94048f0 (patch)
tree14d9f9652ded2b1505299d0a6744457fec1711d8 /drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
parentdrm/amd/display: 3.2.205 (diff)
downloadlinux-dev-e844cc250f33d207077d0af9337484d6c94048f0.tar.xz
linux-dev-e844cc250f33d207077d0af9337484d6c94048f0.zip
drm/amd/display: Refactor LTTPR mode selection
[WHY] Previously, LTTPR mode was decided during detection which makes link training inflexible as mode can't be dynamically changed. [HOW] -Remove lttpr_mode from link struct, and move to link training settings -Defer choosing LTTPR mode until link training Other DP changes included: -Only use fixed vs/pe link training sequence for 8b/10b encoding -Restrict fixed vs aux timeout workaround to Yellow Carp family Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index d01d2eeed813..651231387043 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -35,6 +35,8 @@
#include "dc_link_ddc.h"
#include "dce/dce_aux.h"
#include "dmub/inc/dmub_cmd.h"
+#include "link_dpcd.h"
+#include "include/dal_asic_id.h"
#define DC_LOGGER_INIT(logger)
@@ -683,6 +685,21 @@ bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,
bool result = false;
struct ddc *ddc_pin = ddc->ddc_pin;
+ if ((ddc->link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
+ !ddc->link->dc->debug.disable_fixed_vs_aux_timeout_wa &&
+ ASICREV_IS_YELLOW_CARP(ddc->ctx->asic_id.hw_internal_rev)) {
+ /* Fixed VS workaround for AUX timeout */
+ const uint32_t fixed_vs_address = 0xF004F;
+ const uint8_t fixed_vs_data[4] = {0x1, 0x22, 0x63, 0xc};
+
+ core_link_write_dpcd(ddc->link,
+ fixed_vs_address,
+ fixed_vs_data,
+ sizeof(fixed_vs_data));
+
+ timeout = 3072;
+ }
+
/* Do not try to access nonexistent DDC pin. */
if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY)
return true;
@@ -691,6 +708,7 @@ bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,
ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
result = true;
}
+
return result;
}