diff options
| author |   Ashley Thomas <Ashley.Thomas2@amd.com> | 2020-08-06 19:18:37 -0700 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-09-15 17:52:40 -0400 |
| commit | 172c9b77816549c660aaa79e5df5c1be479f266b (patch) | |
| tree | 9b5b3836588ede57aa43efe3b9d9c84199da84da /drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | |
| parent | drm/amd/display: Fix CP_IRQ clear bit and logic (diff) | |
| download | linux-dev-172c9b77816549c660aaa79e5df5c1be479f266b.tar.xz linux-dev-172c9b77816549c660aaa79e5df5c1be479f266b.zip | |
drm/amd/display: Power eDP panel back ON before link training retry
[why]
When link training failures occur for eDP, dp_disable_link_phy
is called which powers OFF eDP panel. After link training retry
delay, the next retry begins by calling dp_enable_link_phy
which does not issue a correspnding eDP panel power ON, leaving
panel powered OFF which leads to display OFF/dark.
[how]
Power ON eDP before next link training retry.
Signed-off-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index dd88eb348dfa..81c026319ccd 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -104,6 +104,12 @@ void dp_enable_link_phy( struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; unsigned int i; + + if (link->connector_signal == SIGNAL_TYPE_EDP) { + link->dc->hwss.edp_power_control(link, true); + link->dc->hwss.edp_wait_for_hpd_ready(link, true); + } + /* If the current pixel clock source is not DTO(happens after * switching from HDMI passive dongle to DP on the same connector), * switch the pixel clock source to DTO. |