diff options
| author |   Dale Zhao <dale.zhao@amd.com> | 2019-12-02 10:31:55 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-12-18 16:09:10 -0500 |
| commit | 302f598804dc768cd2aa7ed7d6b7bfd326131819 (patch) | |
| tree | 940390a46087fa6e8d4dd6604d71bde0e2762cdd /drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | |
| parent | drm/amd/display: 3.2.64 (diff) | |
| download | linux-dev-302f598804dc768cd2aa7ed7d6b7bfd326131819.tar.xz linux-dev-302f598804dc768cd2aa7ed7d6b7bfd326131819.zip | |
drm/amd/display: Use absolute time stamp to follow the eDP T7 spec requirement
[Why]:
According to eDP spec, max T7 delay should be 50 ms. Current code uses 300
retry counters may not be accurate enough for different panels.
[How]:
Use absolute time stamp to achive accurate delay.
Signed-off-by: Dale Zhao <dale.zhao@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 548aac02ca11..d1df0541e10a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -173,15 +173,20 @@ bool edp_receiver_ready_T9(struct dc_link *link) } bool edp_receiver_ready_T7(struct dc_link *link) { - unsigned int tries = 0; unsigned char sinkstatus = 0; unsigned char edpRev = 0; enum dc_status result = DC_OK; + /* use absolute time stamp to constrain max T7*/ + unsigned long long enter_timestamp = 0; + unsigned long long finish_timestamp = 0; + unsigned long long time_taken_in_ns = 0; + result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev)); if (result == DC_OK && edpRev < DP_EDP_12) return true; /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/ + enter_timestamp = dm_get_timestamp(link->ctx); do { sinkstatus = 0; result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus)); @@ -189,8 +194,10 @@ bool edp_receiver_ready_T7(struct dc_link *link) break; if (result != DC_OK) break; - udelay(25); //MAx T7 is 50ms - } while (++tries < 300); + udelay(25); + finish_timestamp = dm_get_timestamp(link->ctx); + time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, enter_timestamp); + } while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0) udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000); |