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| author |   Alvin Lee <Alvin.Lee2@amd.com> | 2022-09-01 18:40:32 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-09-19 15:12:23 -0400 |
| commit | 6349c73859cba2fabd77494230306ae8a7e45b33 (patch) | |
| tree | c7c8dec17ed7f13c3160cd847091b242ae1aa771 /drivers/gpu/drm/amd/display/dc/core | |
| parent | drm/amd/display: support proper mst payload removal when link is not in mst mode in dc (diff) | |
| download | linux-dev-6349c73859cba2fabd77494230306ae8a7e45b33.tar.xz linux-dev-6349c73859cba2fabd77494230306ae8a7e45b33.zip | |
drm/amd/display: For ODM seamless transition require AUTO mode
[Why & How]
ODM seamless transitions require DIV_MODE_AUTO. However,
DIV_MODE_AUTO only works when all the horizontal timing params
are divisible by the ODM combine factor. Therefore, disable the
ODM 2:1 policy when the horizontal timing params are not divisible
by 2.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 29f27e3fe3ac..5bedee56acd4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -3645,3 +3645,25 @@ const struct link_hwss *get_link_hwss(const struct dc_link *link, else return get_virtual_link_hwss(); } + +bool is_h_timing_divisible_by_2(struct dc_stream_state *stream) +{ + bool divisible = false; + uint16_t h_blank_start = 0; + uint16_t h_blank_end = 0; + + if (stream) { + h_blank_start = stream->timing.h_total - stream->timing.h_front_porch; + h_blank_end = h_blank_start - stream->timing.h_addressable; + + /* HTOTAL, Hblank start/end, and Hsync start/end all must be + * divisible by 2 in order for the horizontal timing params + * to be considered divisible by 2. Hsync start is always 0. + */ + divisible = (stream->timing.h_total % 2 == 0) && + (h_blank_start % 2 == 0) && + (h_blank_end % 2 == 0) && + (stream->timing.h_sync_width % 2 == 0); + } + return divisible; +}
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