diff options
| author |   Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2020-05-21 12:32:53 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:14 -0400 |
| commit | 4d55b0dd1cdd8535ffd6057f210465575117d807 (patch) | |
| tree | fa71c4f5002239f2af3941270bdb519203eba520 /drivers/gpu/drm/amd/display/dc/dc.h | |
| parent | drm/amd/display: Add DCN3 DIO (diff) | |
| download | linux-dev-4d55b0dd1cdd8535ffd6057f210465575117d807.tar.xz linux-dev-4d55b0dd1cdd8535ffd6057f210465575117d807.zip | |
drm/amd/display: Add DCN3 CLK_MGR
Adds support for handling of clocking relevant to the DCN3 block
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ecbdca6d4a79..262da8a4b518 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -459,6 +459,9 @@ struct dc_debug_options { bool disable_tri_buf; bool dmub_offload_enabled; bool dmcub_emulation; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + bool disable_idle_power_optimizations; +#endif bool dmub_command_table; /* for testing only */ struct dc_bw_validation_profile bw_val_profile; bool disable_fec; @@ -572,6 +575,9 @@ struct dc { /* Require to optimize clocks and bandwidth for added/removed planes */ bool optimized_required; bool wm_optimized_required; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + bool idle_optimizations_allowed; +#endif /* Require to maintain clocks and bandwidth for UEFI enabled HW */ int optimize_seamless_boot_streams; @@ -628,6 +634,9 @@ struct dc_init_data { */ const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; struct dpcd_vendor_signature vendor_signature; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + bool force_smu_not_present; +#endif }; struct dc_callback_init { @@ -1198,6 +1207,23 @@ bool dc_is_dmcu_initialized(struct dc *dc); enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + +void dc_allow_idle_optimizations(struct dc *dc, bool allow); + +/* + * blank all streams, and set min and max memory clock to + * lowest and highest DPM level, respectively + */ +void dc_unlock_memory_clock_frequency(struct dc *dc); + +/* + * set min memory clock to the min required for current mode, + * max to maxDPM, and unblank streams + */ +void dc_lock_memory_clock_frequency(struct dc *dc); + +#endif /******************************************************************************* * DSC Interfaces ******************************************************************************/ |