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authorReza Amini <Reza.Amini@amd.com>2020-07-02 16:10:31 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-07-21 15:37:39 -0400
commit831010da1b0b8f0d3e8a5ae4dc81b09947de38f7 (patch)
tree4b3e14a30c4519ab794b704e381e6f0952c91427 /drivers/gpu/drm/amd/display/dc/dc_hw_types.h
parentdrm/amd/display: Add DSC parameters logging to debugfs (diff)
downloadlinux-dev-831010da1b0b8f0d3e8a5ae4dc81b09947de38f7.tar.xz
linux-dev-831010da1b0b8f0d3e8a5ae4dc81b09947de38f7.zip
drm/amd/display: Implement AMD VSIF V3
[Why] To support V3 [How] Generate new VSIF for V3 Signed-off-by: Reza Amini <Reza.Amini@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_hw_types.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_hw_types.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index b7a8c71e3e39..1a87bc3da826 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -713,6 +713,9 @@ struct dc_crtc_timing_flags {
uint32_t LTE_340MCSC_SCRAMBLE:1;
uint32_t DSC : 1; /* Use DSC with this timing */
+#ifndef TRIM_FSFT
+ uint32_t FAST_TRANSPORT: 1;
+#endif
};
enum dc_timing_3d_format {
@@ -772,6 +775,10 @@ struct dc_crtc_timing {
enum dc_aspect_ratio aspect_ratio;
enum scanning_type scan_type;
+#ifndef TRIM_FSFT
+ uint32_t fast_transport_output_rate_100hz;
+#endif
+
struct dc_crtc_timing_flags flags;
struct dc_dsc_config dsc_cfg;
};