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| author |   Alex Deucher <alexander.deucher@amd.com> | 2020-11-02 15:37:34 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-11-04 17:11:37 -0500 |
| commit | 20f2ffe504728612d7b0c34e4f8280e34251e704 (patch) | |
| tree | ab97de569be30e009ba6e5087f3f6c775167e46c /drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | |
| parent | drm/amd/amdgpu: Enable arcturus devices to access the method kgd_gfx_v9_get_cu_occupancy that is already defined (diff) | |
| download | linux-dev-20f2ffe504728612d7b0c34e4f8280e34251e704.tar.xz linux-dev-20f2ffe504728612d7b0c34e4f8280e34251e704.zip | |
drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)
Avoids confusion in configurations.
v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled
v3: rebase on latest code
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_abm.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index dee343f8beb0..456fadbbfac7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -82,7 +82,6 @@ SR(DC_ABM1_ACE_THRES_12), \ NBIO_SR(BIOS_SCRATCH_2) -#if defined(CONFIG_DRM_AMD_DC_DCN3_01) #define ABM_DCN301_REG_LIST(id)\ ABM_COMMON_REG_LIST_DCE_BASE(), \ SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ @@ -96,9 +95,7 @@ SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ NBIO_SR(BIOS_SCRATCH_2) -#endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) #define ABM_DCN30_REG_LIST(id)\ ABM_COMMON_REG_LIST_DCE_BASE(), \ SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ @@ -114,7 +111,6 @@ SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ NBIO_SR(BIOS_SCRATCH_2) -#endif #define ABM_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -189,9 +185,7 @@ #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh) -#endif #define ABM_REG_FIELD_LIST(type) \ type ABM1_HG_NUM_OF_BINS_SEL; \ |