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| author |   Duke Du <Duke.Du@amd.com> | 2017-08-03 10:20:52 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:16:36 -0400 |
| commit | 391e20d84104a6b7b9d4a66fec6a7eb0a93f6ef4 (patch) | |
| tree | c02ff9d55461ffc0db6a64af690c98788ed13930 /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | |
| parent | drm/amd/display: Use atomic types for ref_count (diff) | |
| download | linux-dev-391e20d84104a6b7b9d4a66fec6a7eb0a93f6ef4.tar.xz linux-dev-391e20d84104a6b7b9d4a66fec6a7eb0a93f6ef4.zip | |
drm/amd/display: add display write back(DWB)
Signed-off-by: Duke Du <Duke.Du@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index fc923886e3d4..238c03f14959 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -55,6 +55,8 @@ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRII(PHASE, DP_DTO, 0),\ @@ -71,9 +73,13 @@ SRII(PIXEL_RATE_CNTL, OTG, 3) #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ + CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ + CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) +#endif + #define CS_REG_FIELD_LIST(type) \ type PLL_REF_DIV_SRC; \ type DCCG_DEEP_COLOR_CNTL1; \ @@ -81,6 +87,8 @@ type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \ type PLL_POST_DIV_PIXCLK; \ type PLL_REF_DIV; \ + type DP_DTO0_PHASE; \ + type DP_DTO0_MODULO; \ type DP_DTO0_ENABLE; struct dce110_clk_src_shift { |