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| author |   Tony Cheng <tony.cheng@amd.com> | 2016-12-22 14:54:50 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 17:07:25 -0400 |
| commit | c89a58cd0d1cc940a29a00cc03e441f97fab56e1 (patch) | |
| tree | a1a105f0ddc0f517943ff09882696b1753b0f88e /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | |
| parent | drm/amd/display: Pass adev to fill_plane_attr (diff) | |
| download | linux-dev-c89a58cd0d1cc940a29a00cc03e441f97fab56e1.tar.xz linux-dev-c89a58cd0d1cc940a29a00cc03e441f97fab56e1.zip | |
drm/amd/display: Allow multiple instance of DTO regs
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index 8ee00712ef8e..28984c79fc46 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -76,9 +76,13 @@ struct dce110_clk_src_regs { uint32_t RESYNC_CNTL; uint32_t PIXCLK_RESYNC_CNTL; uint32_t PLL_CNTL; - uint32_t PHASE; - uint32_t MODULO; - uint32_t PIXEL_RATE_CNTL; + + /* below are for DTO. + * todo: should probably use different struct to not waste space + */ + uint32_t PHASE[4]; + uint32_t MODULO[4]; + uint32_t PIXEL_RATE_CNTL[4]; }; struct dce110_clk_src { |