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| author |   Tony Cheng <tony.cheng@amd.com> | 2017-08-03 21:23:04 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:16:23 -0400 |
| commit | 8a5d82451e297fc3864bb9ab0247b53c7ab8a022 (patch) | |
| tree | 366adab8301fc08405c76300a9ef61bd25272010 /drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | |
| parent | drm/amd/display: Fix accessing freed memory (diff) | |
| download | linux-dev-8a5d82451e297fc3864bb9ab0247b53c7ab8a022.tar.xz linux-dev-8a5d82451e297fc3864bb9ab0247b53c7ab8a022.zip | |
drm/amd/display: use some sensible time out
40s time out is not sensible.
also make all udelay poll happen more frequently since CPU is busy anyways
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index aaff946a6d0a..92902f011418 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -262,7 +262,7 @@ static void dce_psr_wait_loop( union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; /* waitDMCUReadyForCmd */ - REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); masterCmdData1.u32 = 0; masterCmdData1.bits.wait_loop = wait_loop_number; @@ -502,7 +502,7 @@ static void dcn10_psr_wait_loop( union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; /* waitDMCUReadyForCmd */ - REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); masterCmdData1.u32 = 0; masterCmdData1.bits.wait_loop = wait_loop_number; |