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| author |   Eryk Brol <eryk.brol@amd.com> | 2019-04-23 11:53:52 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-05-31 10:39:30 -0500 |
| commit | e63e2491ad92036e844230b6373ae07923552f6c (patch) | |
| tree | a783cc66c7acfe858213159d7a5069f87b86adf9 /drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | |
| parent | drm/amd/display: Add GSL source select registers (diff) | |
| download | linux-dev-e63e2491ad92036e844230b6373ae07923552f6c.tar.xz linux-dev-e63e2491ad92036e844230b6373ae07923552f6c.zip | |
drm/amd/display: Ensure DRR triggers in BP
[Why]
In the previous implementation DRR event sometimes came
in during FP2 region which is a keep-out zone. This
would cause the frame not to latch until the next frame
which resulted in heavy flicker. To fix this we need
to make sure that it triggers in the BP.
[How]
1. Remove DRR programming during flip
2. Setup manual trigger for DRR event and trigger it
after surface programming is complete
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c')
0 files changed, 0 insertions, 0 deletions