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| author |   Tony Cheng <tony.cheng@amd.com> | 2017-07-14 14:07:16 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:24 -0400 |
| commit | 2b13d7d380d50811fd4fc022d135c3c5bb70a418 (patch) | |
| tree | 7403a3b3479f8c6e68abba231c98b9ab23b269e0 /drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | |
| parent | drm/amd/display: plumbing to allow easy print of HW state for DTN (diff) | |
| download | linux-dev-2b13d7d380d50811fd4fc022d135c3c5bb70a418.tar.xz linux-dev-2b13d7d380d50811fd4fc022d135c3c5bb70a418.zip | |
drm/amd/display: mpo debug sanity checks
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 94d12b5fb7c6..0479554bc231 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -147,6 +147,9 @@ SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \ SR(REFCLK_CNTL), \ SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), \ + SR(DCHUBBUB_TEST_DEBUG_INDEX), \ + SR(DCHUBBUB_TEST_DEBUG_DATA), \ SR(DC_IP_REQUEST_CNTL), \ SR(DOMAIN0_PG_CONFIG), \ SR(DOMAIN1_PG_CONFIG), \ @@ -195,6 +198,9 @@ struct dce_hwseq_registers { uint32_t OPP_PIPE_CONTROL[4]; uint32_t REFCLK_CNTL; uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; + uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; + uint32_t DCHUBBUB_TEST_DEBUG_INDEX; + uint32_t DCHUBBUB_TEST_DEBUG_DATA; uint32_t DC_IP_REQUEST_CNTL; uint32_t DOMAIN0_PG_CONFIG; uint32_t DOMAIN1_PG_CONFIG; |