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| author |   Yongqiang Sun <yongqiang.sun@amd.com> | 2017-11-24 16:31:03 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2017-12-14 11:00:35 -0500 |
| commit | 904623ee5936e2226009b2f238f28781aecd2565 (patch) | |
| tree | bba0b5b3e1634df87d77ba0949fc75742dd08bf9 /drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | |
| parent | drm/amd/display: fix missing pixel clock adjustment for dongle (diff) | |
| download | linux-dev-904623ee5936e2226009b2f238f28781aecd2565.tar.xz linux-dev-904623ee5936e2226009b2f238f28781aecd2565.zip | |
drm/amd/display: Move wait for hpd ready out from edp power control.
It may take over 200ms for wait hpd ready. To optimize the resume time,
we can power on eDP in init_hw, wait for hpd ready when doing link
training.
also create separate eDP enable function to make sure eDP is powered up
before doing and DPCD access, as HPD low will result in DPDC transaction
failure.
After optimization,
setpowerstate 145ms -> 9.8ms,
DPMS 387ms -> 18.9ms
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index bad70c6b3aad..a266e3f5e75f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1072,21 +1072,6 @@ void dce110_link_encoder_disable_output( /* disable encoder */ if (dc_is_dp_signal(signal)) link_encoder_disable(enc110); - - /* - * TODO: Power control cause regression, we should implement - * it properly, for now just comment it. - */ -// if (enc110->base.connector.id == CONNECTOR_ID_EDP) { -// /* power down eDP panel */ -// link_encoder_edp_wait_for_hpd_ready( -// enc, -// enc->connector, -// false); -// -// link_encoder_edp_power_control( -// enc, false); -// } } void dce110_link_encoder_dp_set_lane_settings( |