drm/amd/display: Flattening core_dc to dc

-Flattening core_dc to dc

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

4 files changed, 22 insertions, 23 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
index 204f613467b7..8816e09110e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
@@ -25,7 +25,6 @@
 
 #include "dm_services.h"
 #include "dc.h"
-#include "core_dc.h"
 #include "core_types.h"
 #include "dce112_hw_sequencer.h"
 
@@ -112,7 +111,7 @@ static void dce112_init_pte(struct dc_context *ctx)
 }
 
 static bool dce112_enable_display_power_gating(
-	struct core_dc *dc,
+	struct dc *dc,
 	uint8_t controller_id,
 	struct dc_bios *dcb,
 	enum pipe_gating_control power_gating)
@@ -153,7 +152,7 @@ static bool dce112_enable_display_power_gating(
 		return false;
 }
 
-bool dce112_hw_sequencer_construct(struct core_dc *dc)
+bool dce112_hw_sequencer_construct(struct dc *dc)
 {
 	/* All registers used by dce11.2 match those in dce11 in offset and
 	 * structure
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
index d96c582da45c..37bd60cc93f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
@@ -28,9 +28,9 @@
 
 #include "core_types.h"
 
-struct core_dc;
+struct dc;
 
-bool dce112_hw_sequencer_construct(struct core_dc *dc);
+bool dce112_hw_sequencer_construct(struct dc *dc);
 
 #endif /* __DC_HWSS_DCE112_H__ */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index d6e58a25f3d0..89a8dfa68c01 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -723,7 +723,7 @@ static struct clock_source *find_matching_pll(
 }
 
 static enum dc_status build_mapped_resource(
-		const struct core_dc *dc,
+		const struct dc *dc,
 		struct validate_context *context,
 		struct validate_context *old_context)
 {
@@ -759,7 +759,7 @@ static enum dc_status build_mapped_resource(
 }
 
 bool dce112_validate_bandwidth(
-	const struct core_dc *dc,
+	struct dc *dc,
 	struct validate_context *context)
 {
 	bool result = false;
@@ -837,7 +837,7 @@ bool dce112_validate_bandwidth(
 }
 
 enum dc_status resource_map_phy_clock_resources(
-		const struct core_dc *dc,
+		const struct dc *dc,
 		struct validate_context *context,
 		struct validate_context *old_context)
 {
@@ -904,7 +904,7 @@ static bool dce112_validate_surface_sets(
 }
 
 enum dc_status dce112_validate_with_context(
-		const struct core_dc *dc,
+		struct dc *dc,
 		const struct dc_validation_set set[],
 		int set_count,
 		struct validate_context *context,
@@ -948,7 +948,7 @@ enum dc_status dce112_validate_with_context(
 }
 
 enum dc_status dce112_validate_guaranteed(
-		const struct core_dc *dc,
+		struct dc *dc,
 		struct dc_stream_state *stream,
 		struct validate_context *context)
 {
@@ -968,7 +968,7 @@ enum dc_status dce112_validate_guaranteed(
 
 	if (result == DC_OK) {
 		validate_guaranteed_copy_streams(
-				context, dc->public.caps.max_streams);
+				context, dc->caps.max_streams);
 		result = resource_build_scaling_params_for_context(dc, context);
 	}
 
@@ -997,7 +997,7 @@ static const struct resource_funcs dce112_res_pool_funcs = {
 	.validate_plane = dce100_validate_plane
 };
 
-static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
+static void bw_calcs_data_update_from_pplib(struct dc *dc)
 {
 	struct dm_pp_clock_levels_with_latency eng_clks = {0};
 	struct dm_pp_clock_levels_with_latency mem_clks = {0};
@@ -1153,7 +1153,7 @@ const struct resource_caps *dce112_resource_cap(
 
 static bool construct(
 	uint8_t num_virtual_links,
-	struct core_dc *dc,
+	struct dc *dc,
 	struct dce110_resource_pool *pool)
 {
 	unsigned int i;
@@ -1170,9 +1170,9 @@ static bool construct(
 	 *************************************************/
 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
-	dc->public.caps.max_downscale_ratio = 200;
-	dc->public.caps.i2c_speed_in_khz = 100;
-	dc->public.caps.max_cursor_size = 128;
+	dc->caps.max_downscale_ratio = 200;
+	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.max_cursor_size = 128;
 
 	/*************************************************
 	 *  Create resources                             *
@@ -1319,7 +1319,7 @@ static bool construct(
 			  &res_create_funcs))
 		goto res_create_fail;
 
-	dc->public.caps.max_planes =  pool->base.pipe_count;
+	dc->caps.max_planes =  pool->base.pipe_count;
 
 	/* Create hardware sequencer */
 	if (!dce112_hw_sequencer_construct(dc))
@@ -1338,7 +1338,7 @@ res_create_fail:
 
 struct resource_pool *dce112_create_resource_pool(
 	uint8_t num_virtual_links,
-	struct core_dc *dc)
+	struct dc *dc)
 {
 	struct dce110_resource_pool *pool =
 		dm_alloc(sizeof(struct dce110_resource_pool));
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
index feef559f1ecd..69f8f689196d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
@@ -28,27 +28,27 @@
 
 #include "core_types.h"
 
-struct core_dc;
+struct dc;
 struct resource_pool;
 
 struct resource_pool *dce112_create_resource_pool(
 	uint8_t num_virtual_links,
-	struct core_dc *dc);
+	struct dc *dc);
 
 enum dc_status dce112_validate_with_context(
-		const struct core_dc *dc,
+		struct dc *dc,
 		const struct dc_validation_set set[],
 		int set_count,
 		struct validate_context *context,
 		struct validate_context *old_context);
 
 enum dc_status dce112_validate_guaranteed(
-		const struct core_dc *dc,
+		struct dc *dc,
 		struct dc_stream_state *dc_stream,
 		struct validate_context *context);
 
 bool dce112_validate_bandwidth(
-	const struct core_dc *dc,
+	struct dc *dc,
 	struct validate_context *context);