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| author |   Dillon Varone <dillon.varone@amd.com> | 2022-04-01 16:45:40 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 16:44:15 -0400 |
| commit | 1908a07cffdfc7c57ba5116418c3f2b5ef05e0f6 (patch) | |
| tree | 291939d2b666cfbcf878e876ef8f1d301b7a5b1c /drivers/gpu/drm/amd/display/dc/dce | |
| parent | drm/amdgpu: print umc correctable error address (diff) | |
| download | linux-dev-1908a07cffdfc7c57ba5116418c3f2b5ef05e0f6.tar.xz linux-dev-1908a07cffdfc7c57ba5116418c3f2b5ef05e0f6.zip | |
drm/amd/display: Select correct DTO source
[WHY&HOW]
Change criteria for setting DTO source value, and always set it regardless of
the signal type.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 845aa8a1027d..4b57657b5322 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -992,7 +992,18 @@ static bool dcn31_program_pix_clk( REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); } +#if defined(CONFIG_DRM_AMD_DC_DCN) + /* Enable DTO */ + if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) + REG_UPDATE_2(PIXEL_RATE_CNTL[inst], + DP_DTO0_ENABLE, 1, + PIPE0_DTO_SRC_SEL, 1); + else + REG_UPDATE(PIXEL_RATE_CNTL[inst], + DP_DTO0_ENABLE, 1); +#else REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); +#endif } else { if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; @@ -1004,10 +1015,26 @@ static bool dcn31_program_pix_clk( REG_WRITE(MODULO[inst], dp_dto_ref_100hz); /* Enable DTO */ + #if defined(CONFIG_DRM_AMD_DC_DCN) + if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) + REG_UPDATE_2(PIXEL_RATE_CNTL[inst], + DP_DTO0_ENABLE, 1, + PIPE0_DTO_SRC_SEL, 1); + else + REG_UPDATE(PIXEL_RATE_CNTL[inst], + DP_DTO0_ENABLE, 1); + #else REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); + #endif return true; } +#if defined(CONFIG_DRM_AMD_DC_DCN) + if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) + REG_UPDATE(PIXEL_RATE_CNTL[inst], + PIPE0_DTO_SRC_SEL, 0); +#endif + /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ bp_pc_params.controller_id = pix_clk_params->controller_id; bp_pc_params.pll_id = clock_source->id; |