diff options
| author |   Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2019-10-25 15:03:58 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-11-13 15:29:42 -0500 |
| commit | 3a1627b07385a6bb497f7ca4e2ffe1e1dbc70b68 (patch) | |
| tree | 03324fc68964444a70a7922a0ba03af277df1c13 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | |
| parent | drm/amdgpu: Add DMCUB to firmware query interface (diff) | |
| download | linux-dev-3a1627b07385a6bb497f7ca4e2ffe1e1dbc70b68.tar.xz linux-dev-3a1627b07385a6bb497f7ca4e2ffe1e1dbc70b68.zip | |
drm/amd/display: Add DMUB support to DC
DC will use DMUB for command submission and flow control during
initialization.
Register offloading as well as submitting some BIOS commands are part
of the DC internal interface but are guarded behind debug options.
It won't be functional in amdgpu_dm yet since we don't pass the
DMUB service to DC for use.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index aa0c7a7d13a0..41a0e53d2ba4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -352,6 +352,9 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, uint32_t i; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); +#ifdef CONFIG_DRM_AMD_DC_DMUB + REG_SEQ_START(); +#endif for (i = 0 ; i < num; i++) { REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); @@ -630,6 +633,10 @@ void dpp1_set_degamma( BREAK_TO_DEBUGGER(); break; } +#ifdef CONFIG_DRM_AMD_DC_DMUB + REG_SEQ_SUBMIT(); + REG_SEQ_WAIT_DONE(); +#endif } void dpp1_degamma_ram_select( |