diff options
| author |   Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2021-05-19 10:58:19 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-06-04 16:39:18 -0400 |
| commit | cbaf919f3313af6a8415076f315d63d0cda1635e (patch) | |
| tree | 388ed410f93f75c8deb32e7c35cece910f05c584 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | |
| parent | drm/amd/display: Add DCN3.1 DCCG (diff) | |
| download | linux-dev-cbaf919f3313af6a8415076f315d63d0cda1635e.tar.xz linux-dev-cbaf919f3313af6a8415076f315d63d0cda1635e.zip | |
drm/amd/display: Add DCN3.1 DIO
Add support for the DIO (Display IO) block of DCN3.1 which controls
legacy HDMI/DP stream/link encoding.
HW Blocks:
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Includes some updates to core logic for link encoder assignment and
future support for new high bandwidth output.
v2: squash in unused variable fix (Alex)
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h index 3e1a582e4b88..ba47553081a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h @@ -160,6 +160,14 @@ struct dcn10_link_enc_registers { uint32_t PHYA_LINK_CNTL2; uint32_t PHYB_LINK_CNTL2; uint32_t PHYC_LINK_CNTL2; +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + uint32_t DIO_LINKA_CNTL; + uint32_t DIO_LINKB_CNTL; + uint32_t DIO_LINKC_CNTL; + uint32_t DIO_LINKD_CNTL; + uint32_t DIO_LINKE_CNTL; + uint32_t DIO_LINKF_CNTL; +#endif }; #define LE_SF(reg_name, field_name, post_fix)\ @@ -459,17 +467,29 @@ struct dcn10_link_enc_registers { type DPCS_TX_DATA_SWAP_10_BIT;\ type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\ type RDPCS_TX_CLK_EN +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) +#define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \ + type ENC_TYPE_SEL;\ + type HPO_DP_ENC_SEL;\ + type HPO_HDMI_ENC_SEL +#endif struct dcn10_link_enc_shift { DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t); DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t); DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t); +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t); +#endif }; struct dcn10_link_enc_mask { DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t); DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t); DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t); +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t); +#endif }; struct dcn10_link_encoder { |