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| author |   Tony Cheng <tony.cheng@amd.com> | 2017-07-12 11:54:10 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:07 -0400 |
| commit | d21becbe0225de0e2582d17d4fbc73fbd103b1f7 (patch) | |
| tree | 32987d555511dcd94b6fbcc4a54c3aa4ca5293dd /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | |
| parent | drm/amd/display: dc_validate_ctx refocunt fixes. (diff) | |
| download | linux-dev-d21becbe0225de0e2582d17d4fbc73fbd103b1f7.tar.xz linux-dev-d21becbe0225de0e2582d17d4fbc73fbd103b1f7.zip | |
drm/amd/display: avoid disabling opp clk before hubp is blanked.
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h index 6a90a8bc09f8..2985c5d5a0e3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h @@ -33,8 +33,7 @@ #define MAX_OPP 6 #define MPC_COMMON_REG_LIST_DCN1_0(inst) \ - SRII(MUX, MPC_OUT, inst),\ - SRII(OPP_PIPE_CONTROL, OPP_PIPE, inst) + SRII(MUX, MPC_OUT, inst) #define MPCC_COMMON_REG_LIST_DCN1_0(inst) \ SRI(MPCC_TOP_SEL, MPCC, inst),\ @@ -56,7 +55,6 @@ struct dcn_mpcc_registers { uint32_t MPCC_BG_G_Y; uint32_t MPCC_BG_R_CR; uint32_t MPCC_BG_B_CB; - uint32_t OPP_PIPE_CONTROL[MAX_OPP]; uint32_t MUX[MAX_OPP]; }; @@ -73,8 +71,7 @@ struct dcn_mpcc_registers { SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\ - SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\ - SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh) + SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh) #define MPCC_REG_FIELD_LIST(type) \ type MPCC_TOP_SEL;\ @@ -90,7 +87,6 @@ struct dcn_mpcc_registers { type MPCC_BG_R_CR;\ type MPCC_BG_B_CB;\ type MPC_OUT_MUX;\ - type OPP_PIPE_CLOCK_EN;\ struct dcn_mpcc_shift { MPCC_REG_FIELD_LIST(uint8_t) |