diff options
| author |   Anthony Koo <Anthony.Koo@amd.com> | 2018-04-11 13:19:56 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2018-05-15 13:44:08 -0500 |
| commit | 388277b17023e69fdbf6ed68cec42fa7616ce454 (patch) | |
| tree | 05979b2b28195f6917744aa91d28529db5012020 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | |
| parent | drm/amd/display: Disallow enabling CRTC without primary plane with FB (diff) | |
| download | linux-dev-388277b17023e69fdbf6ed68cec42fa7616ce454.tar.xz linux-dev-388277b17023e69fdbf6ed68cec42fa7616ce454.zip | |
drm/amd/display: fix issue related to infopacket was not transmitted
Check in code was incorrect, and infopacket is only transmitted after update
function is called multiple times.
Purpose of the function was to check if infopackets are being enabled, and
then enable global control. Fix the code to do this.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c index 9ec46f8fc7cc..befd8639ad55 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c @@ -686,7 +686,7 @@ void enc1_stream_encoder_update_dp_info_packets( const struct encoder_info_frame *info_frame) { struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t value = REG_READ(DP_SEC_CNTL); + uint32_t value = 0; if (info_frame->vsc.valid) enc1_update_generic_info_packet( @@ -713,6 +713,7 @@ void enc1_stream_encoder_update_dp_info_packets( REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); + /* This bit is the master enable bit. * When enabling secondary stream engine, * this master bit must also be set. @@ -720,6 +721,7 @@ void enc1_stream_encoder_update_dp_info_packets( * Therefore we need to enable master bit * if at least on of the fields is not 0 */ + value = REG_READ(DP_SEC_CNTL); if (value) REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); } @@ -729,7 +731,7 @@ void enc1_stream_encoder_stop_dp_info_packets( { /* stop generic packets on DP */ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t value = REG_READ(DP_SEC_CNTL); + uint32_t value = 0; REG_SET_10(DP_SEC_CNTL, 0, DP_SEC_GSP0_ENABLE, 0, @@ -746,7 +748,7 @@ void enc1_stream_encoder_stop_dp_info_packets( /* this register shared with audio info frame. * therefore we need to keep master enabled * if at least one of the fields is not 0 */ - + value = REG_READ(DP_SEC_CNTL); if (value) REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); @@ -1356,7 +1358,7 @@ static void enc1_se_disable_dp_audio( struct stream_encoder *enc) { struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t value = REG_READ(DP_SEC_CNTL); + uint32_t value = 0; /* Disable Audio packets */ REG_UPDATE_5(DP_SEC_CNTL, @@ -1369,6 +1371,7 @@ static void enc1_se_disable_dp_audio( /* This register shared with encoder info frame. Therefore we need to * keep master enabled if at least on of the fields is not 0 */ + value = REG_READ(DP_SEC_CNTL); if (value != 0) REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); |