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author | 2019-10-28 09:22:34 -0400 | |
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committer | 2019-11-13 15:29:42 -0500 | |
commit | 2200eb9e1819aabb9a1c24d5f6b132f389a2e8a9 (patch) | |
tree | b05ea8bcef8f86a29b7b58ff933f8549ecb9b55b /drivers/gpu/drm/amd/display/dc/dcn10 | |
parent | drm/amd/display: Register DMUB service with DC (diff) | |
download | linux-dev-2200eb9e1819aabb9a1c24d5f6b132f389a2e8a9.tar.xz linux-dev-2200eb9e1819aabb9a1c24d5f6b132f389a2e8a9.zip |
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards
[Why]
Support for DMUB only depends on support for DC. It doesn't use floating
point so we don't need to guard it by any specific DCN revision.
[How]
Drop the guards and cleanup the newlines around each one.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 5 |
2 files changed, 3 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 41a0e53d2ba4..6f1a312c6a5a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -352,9 +352,8 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, uint32_t i; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); -#ifdef CONFIG_DRM_AMD_DC_DMUB REG_SEQ_START(); -#endif + for (i = 0 ; i < num; i++) { REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); @@ -633,10 +632,9 @@ void dpp1_set_degamma( BREAK_TO_DEBUGGER(); break; } -#ifdef CONFIG_DRM_AMD_DC_DMUB + REG_SEQ_SUBMIT(); REG_SEQ_WAIT_DONE(); -#endif } void dpp1_degamma_ram_select( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c index 8710f3ac2abf..30c025918568 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c @@ -457,18 +457,15 @@ static bool optc1_enable_crtc(struct timing_generator *optc) REG_UPDATE(CONTROL, VTG0_ENABLE, 1); -#ifdef CONFIG_DRM_AMD_DC_DMUB REG_SEQ_START(); -#endif + /* Enable CRTC */ REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 3, OTG_MASTER_EN, 1); -#ifdef CONFIG_DRM_AMD_DC_DMUB REG_SEQ_SUBMIT(); REG_SEQ_WAIT_DONE(); -#endif return true; } |