diff options
| author |   Harry Wentland <harry.wentland@amd.com> | 2019-02-22 15:50:50 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-06-21 18:59:34 -0500 |
| commit | f7de96ee8b5f4d0d4ef7b00b8868049a6869a10f (patch) | |
| tree | 642f348d5233ecde53fc2422de386c9d2595f311 /drivers/gpu/drm/amd/display/dc/dcn10 | |
| parent | drm/amd/display: Add DCN2 MPC (diff) | |
| download | linux-dev-f7de96ee8b5f4d0d4ef7b00b8868049a6869a10f.tar.xz linux-dev-f7de96ee8b5f4d0d4ef7b00b8868049a6869a10f.zip | |
drm/amd/display: Add DCN2 DPP
Add support to program the DCN2 DPP (Multiple pipe and plane combine)
HW Blocks:
+--------+
| DPP |
+--------+
|
v
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
4 files changed, 27 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 6f4b24756323..b95ec73fcae3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -290,7 +290,12 @@ void dpp1_cnv_setup ( enum surface_pixel_format format, enum expansion_mode mode, struct dc_csc_transform input_csc_color_matrix, +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + enum dc_color_space input_color_space, + struct cnv_alpha_2bit_lut *alpha_2bit_lut) +#else enum dc_color_space input_color_space) +#endif { uint32_t pixel_format; uint32_t alpha_en; @@ -523,6 +528,11 @@ static const struct dpp_funcs dcn10_dpp_funcs = { .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, .dpp_dppclk_control = dpp1_dppclk_control, .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier, +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + .dpp_program_blnd_lut = NULL, + .dpp_program_shaper_lut = NULL, + .dpp_program_3dlut = NULL +#endif }; static struct dpp_caps dcn10_dpp_cap = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 282e22f9b175..8a5517eebb7c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -1486,7 +1486,12 @@ void dpp1_cnv_setup ( enum surface_pixel_format format, enum expansion_mode mode, struct dc_csc_transform input_csc_color_matrix, +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + enum dc_color_space input_color_space, + struct cnv_alpha_2bit_lut *alpha_2bit_lut); +#else enum dc_color_space input_color_space); +#endif void dpp1_full_bypass(struct dpp *dpp_base); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 882bcc5a40f6..aa0c7a7d13a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -731,6 +731,10 @@ void dpp1_full_bypass(struct dpp *dpp_base) /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */ if (dpp->tf_mask->CM_BYPASS_EN) REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1); +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + else + REG_SET(CM_CONTROL, 0, CM_BYPASS, 1); +#endif /* Setting degamma bypass for now */ REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index ce21a290bf3e..d67e0abeee93 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -218,6 +218,14 @@ static void dpp1_dscl_set_lb( INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ } +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + else { + /* DSCL caps: pixel data processed in float format */ + REG_SET_2(LB_DATA_FORMAT, 0, + INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ + LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ + } +#endif REG_SET_2(LB_MEMORY_CTRL, 0, MEMORY_CONFIG, mem_size_config, |