diff options
| author |   Dale Zhao <dale.zhao@amd.com> | 2020-05-29 16:57:02 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:21 -0400 |
| commit | a0a85ac4eac9b1560d9a40d6636f82f81162de10 (patch) | |
| tree | d6e6ad4a591600fbfee4c951a9fb35d128ae0a98 /drivers/gpu/drm/amd/display/dc/dcn20 | |
| parent | drm/amd/display: change global buffer to local buffer (diff) | |
| download | linux-dev-a0a85ac4eac9b1560d9a40d6636f82f81162de10.tar.xz linux-dev-a0a85ac4eac9b1560d9a40d6636f82f81162de10.zip | |
drm/amd/display: Disable pipe split for modes with borders
[Why]
For some special timing with border, like DMT 640*480 72Hz,
pipe split can't handle well. Thus, it will be black screen
for these special timing.
[How]
Disable pipe split for these timing with borders as W/A.
Signed-off-by: Dale Zhao <dale.zhao@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index afa99f967558..fb167393b8fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2666,6 +2666,23 @@ int dcn20_validate_apply_pipe_split_flags( if (plane_count > dc->res_pool->pipe_count / 2) avoid_split = true; + /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct dc_crtc_timing timing; + + if (!pipe->stream) + continue; + else { + timing = pipe->stream->timing; + if (timing.h_border_left + timing.h_border_right + + timing.v_border_top + timing.v_border_bottom > 0) { + avoid_split = true; + break; + } + } + } + /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ if (avoid_split) { for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { |