diff options
| author |   Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2020-05-21 12:44:03 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:14 -0400 |
| commit | db7b0216c4e03bd4cf46edc1b85a7ae159f14703 (patch) | |
| tree | 6067513dae030e03c2e5f4c479cd62d7f2008961 /drivers/gpu/drm/amd/display/dc/dcn20 | |
| parent | drm/amd/display: Add DCN3 HUBHUB (diff) | |
| download | linux-dev-db7b0216c4e03bd4cf46edc1b85a7ae159f14703.tar.xz linux-dev-db7b0216c4e03bd4cf46edc1b85a7ae159f14703.zip | |
drm/amd/display: Add DCN3 HUBP
Add support to program the DCN3 HUBP (Display to data fabric interface
pipe)
HW Blocks:
+--------++------+
| HUBBUB || HUBP |
+--------++------+
|
v
+--------+
| DPP |
+--------+
|
v
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 20 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 41 |
2 files changed, 61 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c index 84d7ac5dd206..bb920d0e0b89 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c @@ -336,6 +336,10 @@ void hubp2_program_size( */ use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + use_pitch_c = use_pitch_c + || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); +#endif if (use_pitch_c) { ASSERT(plane_size->chroma_pitch != 0); /* Chroma pitch zero can cause system hang! */ @@ -360,6 +364,10 @@ void hubp2_program_size( PITCH, pitch, META_PITCH, meta_pitch); use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + use_pitch_c = use_pitch_c + || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); +#endif if (use_pitch_c) REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); @@ -505,6 +513,18 @@ void hubp2_program_pixel_format( REG_UPDATE(DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, 119); break; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + case SURFACE_PIXEL_FORMAT_GRPH_RGBE: + REG_UPDATE_2(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 116, + ALPHA_PLANE_EN, 0); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: + REG_UPDATE_2(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 116, + ALPHA_PLANE_EN, 1); + break; +#endif default: BREAK_TO_DEBUGGER(); break; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h index 8c04a3606a54..4a2c93087459 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h @@ -157,6 +157,12 @@ uint32_t VBLANK_PARAMETERS_5;\ uint32_t VBLANK_PARAMETERS_6 +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#define DCN30_HUBP_REG_COMMON_VARIABLE_LIST \ + DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\ + uint32_t DCN_DMDATA_VM_CNTL +#endif + #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ DCN_HUBP_REG_FIELD_BASE_LIST(type); \ type DMDATA_ADDRESS_HIGH;\ @@ -192,17 +198,52 @@ type REFCYC_PER_META_CHUNK_FLIP_C; \ type VM_GROUP_SIZE +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \ + DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ + type PRIMARY_SURFACE_DCC_IND_BLK;\ + type SECONDARY_SURFACE_DCC_IND_BLK;\ + type PRIMARY_SURFACE_DCC_IND_BLK_C;\ + type SECONDARY_SURFACE_DCC_IND_BLK_C;\ + type ALPHA_PLANE_EN;\ + type REFCYC_PER_VM_DMDATA;\ + type DMDATA_VM_FAULT_STATUS;\ + type DMDATA_VM_FAULT_STATUS_CLEAR; \ + type DMDATA_VM_UNDERFLOW_STATUS;\ + type DMDATA_VM_LATE_STATUS;\ + type DMDATA_VM_UNDERFLOW_STATUS_CLEAR; \ + type DMDATA_VM_DONE; \ + type CROSSBAR_SRC_Y_G; \ + type CROSSBAR_SRC_ALPHA; \ + type PACK_3TO2_ELEMENT_DISABLE; \ + type ROW_TTU_MODE; \ + type NUM_PKRS +#endif struct dcn_hubp2_registers { +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + DCN30_HUBP_REG_COMMON_VARIABLE_LIST; +#else DCN21_HUBP_REG_COMMON_VARIABLE_LIST; +#endif }; struct dcn_hubp2_shift { +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); +#else DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); +#endif + }; struct dcn_hubp2_mask { +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); +#else DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); +#endif + }; struct dcn20_hubp { |