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authorJun Lei <Jun.Lei@amd.com>2019-07-08 15:15:42 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-18 14:27:26 -0500
commit057fc695e934a77bae0c6c7f3be01251774b61cf (patch)
tree405f1311da2b64d9faa06c11f6173c024160acfc /drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
parentdrm/amd/display: fix mpcc assert condition (diff)
downloadlinux-dev-057fc695e934a77bae0c6c7f3be01251774b61cf.tar.xz
linux-dev-057fc695e934a77bae0c6c7f3be01251774b61cf.zip
drm/amd/display: support "dummy pstate"
[why] Existing support in DC for pstate only accounts for a single latency. This is sufficient when the variance of latency is small, or that pstate support isn't necessary for correct ASIC functionality. Newer ASICs violate both existing assumptions. PState support is mandatory of correct ASIC functionality, but not all latencies have to be supported. Existing code supports a "full p state" which allows memory clock to change, but is hard for DCN to support (as it requires very large buffers). New code will now fall back to a "dummy p state" support when "full p state" cannot be support. This easy p state support should always be allowed. [how] Define a new latency in socBB. Add fallback logic to support it. Note DML is also updated to ensure that fallback will always work. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index 91810c7d5cf5..96dfcd8c36bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -28,6 +28,8 @@
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
#include "dcn20/display_mode_vba_20.h"
#include "dcn20/display_rq_dlg_calc_20.h"
+#include "dcn20/display_mode_vba_20v2.h"
+#include "dcn20/display_rq_dlg_calc_20v2.h"
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
@@ -37,6 +39,13 @@ const struct dml_funcs dml20_funcs = {
.rq_dlg_get_dlg_reg = dml20_rq_dlg_get_dlg_reg,
.rq_dlg_get_rq_reg = dml20_rq_dlg_get_rq_reg
};
+
+const struct dml_funcs dml20v2_funcs = {
+ .validate = dml20v2_ModeSupportAndSystemConfigurationFull,
+ .recalculate = dml20v2_recalculate,
+ .rq_dlg_get_dlg_reg = dml20v2_rq_dlg_get_dlg_reg,
+ .rq_dlg_get_rq_reg = dml20v2_rq_dlg_get_rq_reg
+};
#endif
void dml_init_instance(struct display_mode_lib *lib,
@@ -52,6 +61,9 @@ void dml_init_instance(struct display_mode_lib *lib,
case DML_PROJECT_NAVI10:
lib->funcs = dml20_funcs;
break;
+ case DML_PROJECT_NAVI10v2:
+ lib->funcs = dml20v2_funcs;
+ break;
#endif
default:
break;