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authorWenjing Liu <wenjing.liu@amd.com>2022-06-13 11:45:31 -0400
committerAlex Deucher <alexander.deucher@amd.com>2022-07-13 11:25:16 -0400
commit017860c909b03fa687d29a1ca46390ba9a007b2a (patch)
tree27cba141a01ee1849c7998e3180895fd783a112f /drivers/gpu/drm/amd/display/dc/inc/core_status.h
parentdrm/amd/display: Ignore First MST Sideband Message Return Error (diff)
downloadlinux-dev-017860c909b03fa687d29a1ca46390ba9a007b2a.tar.xz
linux-dev-017860c909b03fa687d29a1ca46390ba9a007b2a.zip
drm/amd/display: make enable link independent from verified link caps
[why] Ideally link capability should be independent from the link configuration that we decide to use in enable link. Otherwise if link capability is changed after validation has completed, we could end up enabling a link configuration with invalid configuration. This would lead to over link bandwidth subscription or in the extreme case causes us to enable HPO link to a DIO stream. [how] Add a new struct in pipe ctx called link config. This structure will contain link configuration to enable a link. It will be populated during map pool resources after we validate link bandwidth. Remove the reference of verified link cap during enable link process and use link config in pipe ctx instead. Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/core_status.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/core_status.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 8eb8d4afa876..fa5edd03d004 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -55,6 +55,7 @@ enum dc_status {
DC_NO_LINK_ENC_RESOURCE = 26,
DC_FAIL_DP_PAYLOAD_ALLOCATION = 27,
+ DC_FAIL_DP_LINK_BANDWIDTH = 28,
DC_ERROR_UNEXPECTED = -1
};