diff options
| author |   Yongqiang Sun <yongqiang.sun@amd.com> | 2017-10-10 14:01:33 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2017-10-21 16:51:25 -0400 |
| commit | 62c933f9c6bf287b5b911a1eb838bc942eaa7202 (patch) | |
| tree | 9a40510fedf91338570fe0b88d35c6128aa6846c /drivers/gpu/drm/amd/display/dc/inc/core_status.h | |
| parent | drm/amd/display: Add DIGD case when getting retimer settings (diff) | |
| download | linux-dev-62c933f9c6bf287b5b911a1eb838bc942eaa7202.tar.xz linux-dev-62c933f9c6bf287b5b911a1eb838bc942eaa7202.zip | |
drm/amd/display: WA for 3 display play video hot plug.
Three monitor connected and playing a video will
occupy all 4 pipes, if hot plug forth display,
commit streams will be failed due to no free pipe
can be found.
Work around:
When forth monitor connected, mark video plane as
a fake plane, remove it in dc, keep it in dm and
report address to OS, until OS turn off MPO.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/core_status.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/core_status.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h index b5759c0e5a2f..01df85641684 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h @@ -35,13 +35,14 @@ enum dc_status { DC_FAIL_CONTROLLER_VALIDATE = 5, DC_FAIL_ENC_VALIDATE = 6, DC_FAIL_ATTACH_SURFACES = 7, - DC_FAIL_SURFACE_VALIDATE = 8, - DC_NO_DP_LINK_BANDWIDTH = 9, - DC_EXCEED_DONGLE_MAX_CLK = 10, - DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 11, - DC_FAIL_BANDWIDTH_VALIDATE = 12, /* BW and Watermark validation */ - DC_FAIL_SCALING = 13, - DC_FAIL_DP_LINK_TRAINING = 14, + DC_FAIL_DETACH_SURFACES = 8, + DC_FAIL_SURFACE_VALIDATE = 9, + DC_NO_DP_LINK_BANDWIDTH = 10, + DC_EXCEED_DONGLE_MAX_CLK = 11, + DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 12, + DC_FAIL_BANDWIDTH_VALIDATE = 13, /* BW and Watermark validation */ + DC_FAIL_SCALING = 14, + DC_FAIL_DP_LINK_TRAINING = 15, DC_ERROR_UNEXPECTED = -1 }; |