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| author |   Michael Strauss <michael.strauss@amd.com> | 2021-10-06 15:50:10 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-10-28 14:26:15 -0400 |
| commit | 5fdccd5b88410b6be7f19f3c91ef112d174b1564 (patch) | |
| tree | f6bc8b15ac4e6ad90d0b5f317f70337a43f77d5e /drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | |
| parent | drm/amd/display: Set i2c memory to light sleep during hw init (diff) | |
| download | linux-dev-5fdccd5b88410b6be7f19f3c91ef112d174b1564.tar.xz linux-dev-5fdccd5b88410b6be7f19f3c91ef112d174b1564.zip | |
drm/amd/display: Defer GAMCOR and DSCL power down sequence to vupdate
[WHY]
Every other CM LUT power down sequence is deferred to next vupdate as
memory powerdown updates immediately while selecting LUTs is double
buffered. Previous update to defer LUT power down missed GAMCOR and
DSCL, causing some visible flicker when entering/exiting fullscreen
video playback.
[HOW]
Update dpp deferred update loop to check for valid DPPs in res_pool
instead of referencing dcn_ip which turns out to not be populated during
runtime. Move GAMCOR and DSCL powerdown to dpp deferred updates.
Reviewed-by: Haonan Wang <Haonan.Wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 9f12792b7e59..3ef7faa92052 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -34,6 +34,8 @@ union defer_reg_writes { bool disable_blnd_lut:1; bool disable_3dlut:1; bool disable_shaper:1; + bool disable_gamcor:1; + bool disable_dscl:1; } bits; uint32_t raw; }; |