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| author |   Lang Yu <Lang.Yu@amd.com> | 2022-01-24 14:25:34 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-01-25 18:00:34 -0500 |
| commit | d435c1ed56b9f9347189924395588cfdf7489af5 (patch) | |
| tree | 4a35248fdbfca8cfb8bd0dec40b6985b79ea1fd8 /drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h | |
| parent | Revert "drm/amdgpu: No longer insert ras blocks into ras_list if it already exists in ras_list" (diff) | |
| download | linux-dev-d435c1ed56b9f9347189924395588cfdf7489af5.tar.xz linux-dev-d435c1ed56b9f9347189924395588cfdf7489af5.zip | |
drm/amd/pm: add get_dpm_ultimate_freq function for cyan skillfish
Some clients(e.g., kfd) query sclk/mclk through this function.
As cyan skillfish doesn't support dpm, for sclk, set min/max
to CYAN_SKILLFISH_SCLK_MIN/CYAN_SKILLFISH_SCLK_MAX(to maintain the
existing logic).For others, set both min and max to current value.
Before this patch:
# /opt/rocm/opencl/bin/clinfo
Max clock frequency: 0Mhz
After this patch:
# /opt/rocm/opencl/bin/clinfo
Max clock frequency: 2000Mhz
v2:
- Maintain the existing min/max sclk logic.(Lijo)
v3:
- Avoid fetching metrics table twice.(Lijo)
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h')
0 files changed, 0 insertions, 0 deletions