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| author |   Martin Leung <martin.leung@amd.com> | 2019-07-17 16:08:19 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-08-15 10:54:27 -0500 |
| commit | 5ec43eda85506ddc2f91c3a4e28b38da3f14cf1e (patch) | |
| tree | 62aa9ea986f025062d7ed0dd8b45708aca89af26 /drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | |
| parent | drm/amd/display: fix dcn-specific clk_mgr init_clocks (diff) | |
| download | linux-dev-5ec43eda85506ddc2f91c3a4e28b38da3f14cf1e.tar.xz linux-dev-5ec43eda85506ddc2f91c3a4e28b38da3f14cf1e.zip | |
drm/amd/display: enabling seamless boot sequence for dcn2
[Why]
Seamless boot (building SW state inheriting BIOS-initialized timing) was
enabled on DCN2, including fixes
[How]
Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
Pixel clock.
This is part 2 of 2 for seamless boot NV10
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 9f00289bda78..9dde88d4571c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -199,6 +199,9 @@ struct mpc_funcs { * Return: void */ void (*mpc_init)(struct mpc *mpc); + void (*mpc_init_single_inst)( + struct mpc *mpc, + unsigned int mpcc_id); /* * Update the blending configuration for a specified MPCC. |