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author | Yongqiang Sun <yongqiang.sun@amd.com> | 2019-02-15 17:05:43 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-03-19 15:36:49 -0500 |
commit | 30eb85ff422f1cf97ca35f37aef7a1cd77744cce (patch) | |
tree | cd73f5d66165da34f95afc91697754cb226ed8f9 /drivers/gpu/drm/amd/display/dc/inc/reg_helper.h | |
parent | drm/amd/display: Add PSR SMU Interrupt support (diff) | |
download | linux-dev-30eb85ff422f1cf97ca35f37aef7a1cd77744cce.tar.xz linux-dev-30eb85ff422f1cf97ca35f37aef7a1cd77744cce.zip |
drm/amd/display: Combine field toggle macro and sequence write macro.
[Why]
field toggle write is actual field sequence write with the same
field name.
[How]
Use REG_UPDATE_SEQ_2 for both sequence write and toggle.
Rename REG_UPDATE_1by1_3 to REG_UPDATE_SEQ_3.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/reg_helper.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/reg_helper.h | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h index 3768245a3602..8503d9cc4763 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h +++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h @@ -379,16 +379,11 @@ /* macro to update a register field to specified values in given sequences. * useful when toggling bits */ -#define REG_UPDATE_SEQ(reg, field, value1, value2) \ -{ uint32_t val = REG_UPDATE(reg, field, value1); \ - REG_SET(reg, val, field, value2); } - -/* macro to update fields in register 1 field at a time in given order */ -#define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \ +#define REG_UPDATE_SEQ_2(reg, f1, v1, f2, v2) \ { uint32_t val = REG_UPDATE(reg, f1, v1); \ REG_SET(reg, val, f2, v2); } -#define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \ +#define REG_UPDATE_SEQ_3(reg, f1, v1, f2, v2, f3, v3) \ { uint32_t val = REG_UPDATE(reg, f1, v1); \ val = REG_SET(reg, val, f2, v2); \ REG_SET(reg, val, f3, v3); } |