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| author |   Jun Lei <jun.lei@amd.com> | 2020-05-26 11:17:53 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:20 -0400 |
| commit | 0a25e8eb95cd7bf28857ef671296154c25b1fb44 (patch) | |
| tree | d6da45a57034e164e113545df943d64b3c254027 /drivers/gpu/drm/amd/display/dc/inc | |
| parent | drm/amd/display: Revert "DP link layer test 4.2.1.1 fix due to specs update" (diff) | |
| download | linux-dev-0a25e8eb95cd7bf28857ef671296154c25b1fb44.tar.xz linux-dev-0a25e8eb95cd7bf28857ef671296154c25b1fb44.zip | |
drm/amd/display: add support for per-state dummy-pstate latency
[why]
Dummy pstate latency actually varies between different
UCLK frequencies, when calculating watermark C, if DAL
always assumes worst case, then it can lead to dummy
pstate not supported scenarios.
[how]
Rather than statically calculating dummy pstate using
worst case, we store the entire table of UCLK to dummy
pstate relationships. On a per mode basis, we calculate
the actual UCLK lower limit, and use the dynamic worst
case dummy pstate latency. This prevents the situation
where we don't support full p-state (which will force
high DPM), but still use low DPM dummy pstate latency.
Signed-off-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 49c50af9cd9e..505357597603 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -198,11 +198,17 @@ struct wm_table { #endif }; +struct dummy_pstate_entry { + unsigned int dram_speed_mts; + unsigned int dummy_pstate_latency_us; +}; + struct clk_bw_params { unsigned int vram_type; unsigned int num_channels; struct clk_limit_table clk_table; struct wm_table wm_table; + struct dummy_pstate_entry dummy_pstate_table[4]; }; /* Public interfaces */ |