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authorReza Amini <Reza.Amini@amd.com>2020-07-15 11:33:23 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-08-06 16:40:18 -0400
commit471c1dd9546df81d259664ac3e2ab0e99169f755 (patch)
tree9c7dfcbbaeedbe03a8cd923733a09745e289d774 /drivers/gpu/drm/amd/display/dc/inc
parentdrm/amd/display: Disable idle optimizations before programming DCN (diff)
downloadlinux-dev-471c1dd9546df81d259664ac3e2ab0e99169f755.tar.xz
linux-dev-471c1dd9546df81d259664ac3e2ab0e99169f755.zip
drm/amd/display: Allow asic specific FSFT timing optimization
[Why] Each asic can optimize best based on its capabilities [How] Optimizing timing for a new pixel clock Signed-off-by: Reza Amini <Reza.Amini@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 720ce5e458d8..3c986717dcd5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -116,6 +116,11 @@ struct hw_sequencer_funcs {
void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
int num_pipes,
const struct dc_static_screen_params *events);
+#ifndef TRIM_FSFT
+ bool (*optimize_timing_for_fsft)(struct dc *dc,
+ struct dc_crtc_timing *timing,
+ unsigned int max_input_rate_in_khz);
+#endif
/* Stream Related */
void (*enable_stream)(struct pipe_ctx *pipe_ctx);