diff options
author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2020-05-21 12:32:53 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:14 -0400 |
commit | 4d55b0dd1cdd8535ffd6057f210465575117d807 (patch) | |
tree | fa71c4f5002239f2af3941270bdb519203eba520 /drivers/gpu/drm/amd/display/dc/inc | |
parent | drm/amd/display: Add DCN3 DIO (diff) | |
download | linux-dev-4d55b0dd1cdd8535ffd6057f210465575117d807.tar.xz linux-dev-4d55b0dd1cdd8535ffd6057f210465575117d807.zip |
drm/amd/display: Add DCN3 CLK_MGR
Adds support for handling of clocking relevant to the DCN3 block
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 69 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 14 |
2 files changed, 83 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index ce65678c03b2..49c50af9cd9e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -43,6 +43,25 @@ #define DCN_MINIMUM_DISPCLK_Khz 100000 #define DCN_MINIMUM_DPPCLK_Khz 100000 +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +struct dcn3_clk_internal { + int dummy; + /*TODO: + uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk + uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk + uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk + uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk + uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider + uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow + + uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass + uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass + uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass + uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass + */ +}; + +#endif /* Will these bw structures be ASIC specific? */ #define MAX_NUM_DPM_LVL 8 @@ -55,6 +74,12 @@ struct clk_limit_table_entry { unsigned int fclk_mhz; unsigned int memclk_mhz; unsigned int socclk_mhz; +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + unsigned int dtbclk_mhz; + unsigned int dispclk_mhz; + unsigned int dppclk_mhz; + unsigned int phyclk_mhz; +#endif }; /* This table is contiguous */ @@ -72,6 +97,26 @@ struct wm_range_table_entry { bool valid; }; +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + +struct nv_wm_range_entry { + bool valid; + + struct { + uint8_t wm_type; + uint16_t min_dcfclk; + uint16_t max_dcfclk; + uint16_t min_uclk; + uint16_t max_uclk; + } pmfw_breakdown; + + struct { + double pstate_latency_us; + double sr_exit_time_us; + double sr_enter_plus_exit_time_us; + } dml_input; +}; +#endif struct clk_log_info { bool enabled; @@ -143,7 +188,14 @@ struct clk_bypass { * D occupied, C will be emptry. */ struct wm_table { +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + union { + struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; +#endif struct wm_range_table_entry entries[WM_SET_COUNT]; +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + }; +#endif }; struct clk_bw_params { @@ -183,6 +235,20 @@ struct clk_mgr_funcs { bool (*are_clock_states_equal) (struct dc_clocks *a, struct dc_clocks *b); void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + /* + * Send message to PMFW to set hard min memclk frequency + * When current_mode = false, set DPM0 + * When current_mode = true, set required clock for current mode + */ + void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode); + + /* Send message to PMFW to set hard max memclk frequency to highest DPM */ + void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr); + + /* Get current memclk states from PMFW, update relevant structures */ + void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); +#endif }; struct clk_mgr { @@ -190,6 +256,9 @@ struct clk_mgr { struct clk_mgr_funcs *funcs; struct dc_clocks clks; bool psr_allow_active_cache; +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + bool force_smu_not_present; +#endif int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes int dentist_vco_freq_khz; struct clk_state_registers_and_bypass boot_snapshot; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index 9311d0de377f..c3c151be7d03 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -101,6 +101,12 @@ enum dentist_divider_range { CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \ CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0) +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 +// TODO: +#define CLK_REG_LIST_DCN3() \ + SR(DENTIST_DISPCLK_CNTL) +#endif + #define CLK_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -167,6 +173,10 @@ struct clk_mgr_registers { uint32_t CLK3_CLK2_DFS_CNTL; uint32_t CLK3_CLK_PLL_REQ; +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + uint32_t CLK0_CLK2_DFS_CNTL; + uint32_t CLK0_CLK_PLL_REQ; +#endif uint32_t MP1_SMN_C2PMSG_67; uint32_t MP1_SMN_C2PMSG_83; uint32_t MP1_SMN_C2PMSG_91; @@ -260,6 +270,10 @@ struct clk_mgr_internal { enum dm_pp_clocks_state max_clks_state; enum dm_pp_clocks_state cur_min_clks_state; +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + + bool smu_present; +#endif }; struct clk_mgr_internal_funcs { |