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| author |   Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2020-05-21 12:51:51 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:15 -0400 |
| commit | 5dba4991fd338dc4b2664c0c6b3d80edead4e22c (patch) | |
| tree | f5058af4d7a61aed90327192c283c76659ae59d2 /drivers/gpu/drm/amd/display/dc/inc | |
| parent | drm/amd/display: Add DCN3 Support in DM (v2) (diff) | |
| download | linux-dev-5dba4991fd338dc4b2664c0c6b3d80edead4e22c.tar.xz linux-dev-5dba4991fd338dc4b2664c0c6b3d80edead4e22c.zip | |
drm/amd/display: Add DCN3 Resource
Add support for managing resources for DCN3
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/core_types.h | 21 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 |
3 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 654dcdb4aba6..4fbed8dd0c59 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -147,6 +147,20 @@ struct resource_funcs { void (*update_bw_bounding_box)( struct dc *dc, struct clk_bw_params *bw_params); +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + bool (*acquire_post_bldn_3dlut)( + struct resource_context *res_ctx, + const struct resource_pool *pool, + int mpcc_id, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper); + + bool (*release_post_bldn_3dlut)( + struct resource_context *res_ctx, + const struct resource_pool *pool, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper); +#endif }; @@ -189,6 +203,10 @@ struct resource_pool { unsigned int underlay_pipe_index; unsigned int stream_enc_count; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + struct dc_3dlut *mpc_lut[MAX_PIPES]; + struct dc_transfer_func *mpc_shaper[MAX_PIPES]; +#endif struct { unsigned int xtalin_clock_inKhz; unsigned int dccg_ref_clock_inKhz; @@ -316,6 +334,9 @@ struct resource_context { uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; uint8_t dp_clock_source_ref_count; bool is_dsc_acquired[MAX_PIPES]; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + bool is_mpc_3dlut_acquired[MAX_PIPES]; +#endif }; struct dce_bw_output { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 75d419081e76..f62ccf242f56 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -150,6 +150,15 @@ enum ipp_degamma_mode { IPP_DEGAMMA_MODE_USER_PWL }; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +enum gamcor_mode { + GAMCOR_MODE_BYPASS, + GAMCOR_MODE_RESERVED_1, + GAMCOR_MODE_USER_PWL, + GAMCOR_MODE_RESERVED_3 +}; +#endif + enum ipp_output_format { IPP_OUTPUT_FORMAT_12_BIT_FIX, IPP_OUTPUT_FORMAT_16_BIT_BYPASS, diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index a9be495af922..dbd74d548de3 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -48,6 +48,9 @@ struct resource_caps { int num_ddc; int num_vmid; int num_dsc; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + int num_mpc_3dlut; +#endif }; struct resource_straps { |