diff options
| author |   Charlene Liu <charlene.liu@amd.com> | 2019-06-27 18:16:21 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 14:27:25 -0500 |
| commit | 925f566cb7aedbcf26005035cf894ec824e8ca2f (patch) | |
| tree | 06f5ac58c76e29af2bfce31f2adbf3787ae7bbda /drivers/gpu/drm/amd/display/dc/inc | |
| parent | drm/amd/display: allocate 4 ddc engines for RV2 (diff) | |
| download | linux-dev-925f566cb7aedbcf26005035cf894ec824e8ca2f.tar.xz linux-dev-925f566cb7aedbcf26005035cf894ec824e8ca2f.zip | |
drm/amd/display: add set and get clock for testing purposes
add dc_set_clock
add dc_get_clock
this is for testing and diagnostics to get/set DPPCLK and DISPCLK.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/core_status.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 9 |
3 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h index 0a094d7c9380..fd39e2abe2ed 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h @@ -48,6 +48,9 @@ enum dc_status { DC_NO_DSC_RESOURCE = 17, #endif DC_FAIL_UNSUPPORTED_1 = 18, + DC_FAIL_CLK_EXCEED_MAX = 21, + DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/ + DC_FAIL_CLK_BELOW_CFG_REQUIRED = 23, /*THIS IS hard_min in PPLIB*/ DC_ERROR_UNEXPECTED = -1 }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 36ebd5bc7863..938bdc5c21a1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -28,6 +28,9 @@ #include "dc.h" +#define DCN_MINIMUM_DISPCLK_Khz 100000 +#define DCN_MINIMUM_DPPCLK_Khz 100000 + /* Public interfaces */ struct clk_states { @@ -51,6 +54,10 @@ struct clk_mgr_funcs { void (*init_clocks)(struct clk_mgr *clk_mgr); void (*enable_pme_wa) (struct clk_mgr *clk_mgr); + void (*get_clock)(struct clk_mgr *clk_mgr, + struct dc_state *context, + enum dc_clock_type clock_type, + struct dc_clock_config *clock_cfg); }; struct clk_mgr { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 4d56d48a3179..36be08adae05 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -294,6 +294,15 @@ struct hw_sequencer_funcs { void (*disable_writeback)(struct dc *dc, unsigned int dwb_pipe_inst); #endif + enum dc_status (*set_clock)(struct dc *dc, + enum dc_clock_type clock_type, + uint32_t clk_khz, + uint32_t stepping); + + void (*get_clock)(struct dc *dc, + enum dc_clock_type clock_type, + struct dc_clock_config *clock_cfg); + }; void color_space_to_black_color( |