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| author |   Eryk Brol <eryk.brol@amd.com> | 2019-04-23 11:53:52 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:07 -0500 |
| commit | ae8f425840cb642873ff97b7a6711aad42766133 (patch) | |
| tree | 7baba01f5cf88df7585e65ccc16bbdba028d0ba6 /drivers/gpu/drm/amd/display/dc/inc | |
| parent | drm/amd/display/dc: fix azalia workaround sw implementation bug (diff) | |
| download | linux-dev-ae8f425840cb642873ff97b7a6711aad42766133.tar.xz linux-dev-ae8f425840cb642873ff97b7a6711aad42766133.zip | |
drm/amd/display: Ensure DRR triggers in BP
[Why]
In the previous implementation DRR event sometimes came
in during FP2 region which is a keep-out zone. This
would cause the frame not to latch until the next frame
which resulted in heavy flicker. To fix this we need
to make sure that it triggers in the BP.
[How]
1. Remove DRR programming during flip
2. Setup manual trigger for DRR event and trigger it
after surface programming is complete
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index eced6ec05899..251baebe5386 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -257,6 +257,7 @@ struct timing_generator_funcs { void (*set_vtg_params)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); + #ifdef CONFIG_DRM_AMD_DC_DCN2_0 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void (*set_dsc_config)(struct timing_generator *optc, |