diff options
| author |   Fangzhi Zuo <Jerry.Zuo@amd.com> | 2021-08-03 18:46:00 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-09-01 16:55:10 -0400 |
| commit | f01ee019586220c86f238263a4fbde6e72085e11 (patch) | |
| tree | 7cc06dedf7dbae7cec4f779cfd9a393d1eef2f9f /drivers/gpu/drm/amd/display/dc/inc | |
| parent | drm/amd/display: Add DP 2.0 BIOS and DMUB Support (diff) | |
| download | linux-dev-f01ee019586220c86f238263a4fbde6e72085e11.tar.xz linux-dev-f01ee019586220c86f238263a4fbde6e72085e11.zip | |
drm/amd/display: Add DP 2.0 SST DC Support
1. Retrieve 128/132b link cap.
2. 128/132b link training and payload allocation.
3. UHBR10 link rate support.
[squash in warning fixes - Alex]
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 22 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/resource.h | 5 |
3 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index 01c3a31be191..3cc110e13213 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -30,6 +30,7 @@ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ #define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/ #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/ +#define MAX_MTP_SLOT_COUNT 64 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 #define TRAINING_AUX_RD_INTERVAL 100 //us @@ -189,5 +190,26 @@ enum dc_status dpcd_configure_lttpr_mode( struct link_training_settings *lt_settings); enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings); +bool dpcd_write_128b_132b_sst_payload_allocation_table( + const struct dc_stream_state *stream, + struct dc_link *link, + struct link_mst_stream_allocation_table *proposed_table, + bool allocate); + +enum dc_status dpcd_configure_channel_coding( + struct dc_link *link, + struct link_training_settings *lt_settings); + +bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link); + +struct fixed31_32 calculate_sst_avg_time_slots_per_mtp( + const struct dc_stream_state *stream, + const struct dc_link *link); +void enable_dp_hpo_output(struct dc_link *link, const struct dc_link_settings *link_settings); +void disable_dp_hpo_output(struct dc_link *link, enum signal_type signal); +void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable); +bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx); +void reset_dp_hpo_stream_encoders_for_link(struct dc_link *link); + bool dp_retrieve_lttpr_cap(struct dc_link *link); #endif /* __DC_LINK_DP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h index f7f7e4fff0c2..d09eed7bcc4a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h @@ -41,6 +41,9 @@ struct dce_hwseq_wa { bool DEGVIDCN10_254; bool DEGVIDCN21; bool disallow_self_refresh_during_multi_plane_transition; +#if defined(CONFIG_DRM_AMD_DC_DCN) + bool dp_hpo_and_otg_sequence; +#endif }; struct hwseq_wa_state { diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 713f6d5cf3e0..3fbda9d7e257 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -200,4 +200,9 @@ int get_num_mpc_splits(struct pipe_ctx *pipe); int get_num_odm_splits(struct pipe_ctx *pipe); +#if defined(CONFIG_DRM_AMD_DC_DCN) +struct hpo_dp_link_encoder *resource_get_unused_hpo_dp_link_encoder( + const struct resource_pool *pool); +#endif + #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ |