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| author |   Eric Bernstein <eric.bernstein@amd.com> | 2018-07-30 17:43:23 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-07-05 16:16:43 -0400 |
| commit | c1127df9515ca781940927deffc5ae657ed73a5f (patch) | |
| tree | c5f49c697dcab6459505a2a1eaaf09de987b9aea /drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |
| parent | drm/amd/display: Add flag to modify MST delay (diff) | |
| download | linux-dev-c1127df9515ca781940927deffc5ae657ed73a5f.tar.xz linux-dev-c1127df9515ca781940927deffc5ae657ed73a5f.zip | |
drm/amd/display: Fix null timing generator resource
[Why]
For some customer blending transition cases, the
available pipe for second stream is a pipe index that is
greater than the number of timing generators, which
can cause a problem in acquire_first_free_pipe since it
assumes same index for pipe and timing generator
[How]
Added logic to use last timing generator index
if the pipe index is greater than number of timing generators.
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c')
0 files changed, 0 insertions, 0 deletions