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| author |   Alex Deucher <alexander.deucher@amd.com> | 2021-06-21 16:51:30 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-22 16:51:45 -0400 |
| commit | 8fe44c080a53ac0ccbe88053a2e40f9acca33091 (patch) | |
| tree | a2d024cbfbf3c1f27b0312843c373fcdf0441b6c /drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h | |
| parent | drm/radeon: delete useless function return values & remove meaningless if(r) check code (diff) | |
| download | linux-dev-8fe44c080a53ac0ccbe88053a2e40f9acca33091.tar.xz linux-dev-8fe44c080a53ac0ccbe88053a2e40f9acca33091.zip | |
drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN
No need for a separate flag now that DCN3.1 is not in bring up.
Fold into DRM_AMD_DC_DCN like previous DCN IPs.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h index b0b2544eaa9d..2937b4b61461 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h @@ -44,12 +44,8 @@ enum bgd_security_hdcp2_content_type { enum ta_dtm_command { TA_DTM_COMMAND__UNUSED_1 = 1, TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2, -#if defined(CONFIG_DRM_AMD_DC_DCN3_1) TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE, TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3 -#else - TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE -#endif }; /* DTM related enumerations */ @@ -91,7 +87,6 @@ struct ta_dtm_topology_update_input_v2 { uint32_t max_hdcp_supported_version; }; -#if defined(CONFIG_DRM_AMD_DC_DCN3_1) /* For security reason/HW may change value, these encoder type enum values are not HW register values */ /* Security code will check real HW register values and these SW enum values */ enum ta_dtm_encoder_type { @@ -117,7 +112,7 @@ struct ta_dtm_topology_update_input_v3 { uint32_t phy_id; uint32_t link_hdcp_cap; }; -#endif + struct ta_dtm_topology_assr_enable { uint32_t display_topology_dig_be_index; }; @@ -131,9 +126,7 @@ struct ta_dtm_topology_assr_enable { union ta_dtm_cmd_input { struct ta_dtm_topology_update_input_v2 topology_update_v2; struct ta_dtm_topology_assr_enable topology_assr_enable; -#if defined(CONFIG_DRM_AMD_DC_DCN3_1) struct ta_dtm_topology_update_input_v3 topology_update_v3; -#endif }; union ta_dtm_cmd_output { @@ -313,10 +306,8 @@ enum ta_hdcp2_version { TA_HDCP2_VERSION_UNKNOWN = 0, TA_HDCP2_VERSION_2_0 = 20, TA_HDCP2_VERSION_2_1 = 21, -#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + TA_HDCP2_VERSION_2_2 = 22, TA_HDCP2_VERSION_2_3 = 23, -#endif - TA_HDCP2_VERSION_2_2 = 22 }; /* input/output structures for HDCP commands */ |