diff options
| author |   Murton Liu <murton.liu@amd.com> | 2019-06-10 17:55:28 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 14:17:19 -0500 |
| commit | 492d9ec244923420af96db6b69ad7d575859aa92 (patch) | |
| tree | 01e18dcbc8aba19c326efb7ad0443f2ac62f9797 /drivers/gpu/drm/amd/display | |
| parent | drm/amd/display: skip retrain in dc_link_set_preferred_link_settings() if using passive dongle (diff) | |
| download | linux-dev-492d9ec244923420af96db6b69ad7d575859aa92.tar.xz linux-dev-492d9ec244923420af96db6b69ad7d575859aa92.zip | |
drm/amd/display: Clock does not lower in Updateplanes
[why]
We reset the optimized_required in atomic_plane_disable
flag immediately after it is set in atomic_plane_disconnect, causing us to
never have flag set during next flip in UpdatePlanes.
[how]
Optimize directly after each time plane is removed.
Signed-off-by: Murton Liu <murton.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e50a696fcb5d..0c4340404e24 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2516,6 +2516,12 @@ static void dcn10_apply_ctx_for_surface( if (removed_pipe[i]) dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); + for (i = 0; i < dc->res_pool->pipe_count; i++) + if (removed_pipe[i]) { + dc->hwss.optimize_bandwidth(dc, context); + break; + } + if (dc->hwseq->wa.DEGVIDCN10_254) hubbub1_wm_change_req_wa(dc->res_pool->hubbub); } |