diff options
| author |   Maxime Ripard <mripard@kernel.org> | 2019-10-03 09:59:29 +0200 |
|---|---|---|
| committer | Maxime Ripard <mripard@kernel.org> | 2019-10-03 09:59:29 +0200 |
| commit | 77fdaa091d79c87323a9f3912a25f73e02ea2a01 (patch) | |
| tree | 0e47e2d3c4a966277dbaec075f4685187fdae482 /drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h | |
| parent | drm/omap: fix max fclk divider for omap36xx (diff) | |
| parent | Linux 5.4-rc1 (diff) | |
| download | linux-dev-77fdaa091d79c87323a9f3912a25f73e02ea2a01.tar.xz linux-dev-77fdaa091d79c87323a9f3912a25f73e02ea2a01.zip | |
Merge drm/drm-fixes into drm-misc-fixes
We haven't backmerged for a while, let's start the -rc period by pulling
rc1.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h index 8f515875a34d..f2ae3a58949e 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h @@ -21,6 +21,27 @@ #ifndef _mmhub_9_4_0_OFFSET_HEADER #define _mmhub_9_4_0_OFFSET_HEADER +/* MMEA */ +#define mmMMEA0_SDP_ARB_FINAL_VG20 0x01ee +#define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX 0 +#define mmMMEA0_EDC_CNT_VG20 0x0206 +#define mmMMEA0_EDC_CNT_VG20_BASE_IDX 0 +#define mmMMEA0_EDC_CNT2_VG20 0x0207 +#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX 0 +#define mmMMEA0_EDC_MODE_VG20 0x0210 +#define mmMMEA0_EDC_MODE_VG20_BASE_IDX 0 +#define mmMMEA0_ERR_STATUS_VG20 0x0211 +#define mmMMEA0_ERR_STATUS_VG20_BASE_IDX 0 +#define mmMMEA1_SDP_ARB_FINAL_VG20 0x032e +#define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX 0 +#define mmMMEA1_EDC_CNT_VG20 0x0346 +#define mmMMEA1_EDC_CNT_VG20_BASE_IDX 0 +#define mmMMEA1_EDC_CNT2_VG20 0x0347 +#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX 0 +#define mmMMEA1_EDC_MODE_VG20 0x0350 +#define mmMMEA1_EDC_MODE_VG20_BASE_IDX 0 +#define mmMMEA1_ERR_STATUS_VG20 0x0351 +#define mmMMEA1_ERR_STATUS_VG20_BASE_IDX 0 // addressBlock: mmhub_utcl2_vmsharedpfdec // base address: 0x6a040 |