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authorAlex Deucher <alexander.deucher@amd.com>2022-05-26 11:55:36 -0400
committerAlex Deucher <alexander.deucher@amd.com>2022-06-03 16:45:00 -0400
commitda1db031cd30fefc99d1c82211d3c24b73857bbe (patch)
tree5969c18b8abdb87f53899e47c929b962ba0dd2ad /drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
parentdrm/amd/display: Disable DTB Ref Clock Switching in dcn32 (diff)
downloadlinux-dev-da1db031cd30fefc99d1c82211d3c24b73857bbe.tar.xz
linux-dev-da1db031cd30fefc99d1c82211d3c24b73857bbe.zip
drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
So we can eventaully use them in the common smu code for accessing the SMU mailboxes without needing a lot of per asic logic in the common code. Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c')
-rw-r--r--drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 1c5ce9c5cba9..b71860e5324a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -4357,4 +4357,5 @@ void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
smu->table_map = sienna_cichlid_table_map;
smu->pwr_src_map = sienna_cichlid_pwr_src_map;
smu->workload_map = sienna_cichlid_workload_map;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}