diff options
| author |   Tom St Denis <tom.stdenis@amd.com> | 2016-09-30 10:58:44 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2016-10-25 14:38:25 -0400 |
| commit | 97f40ef049dded1962bc9e70ad4d197fa8a5cadb (patch) | |
| tree | f6edd8d9535a625fdb159c300148106cbaf07520 /drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c | |
| parent | drm/amdgpu: update the shadow PD together with the real one v2 (diff) | |
| download | linux-dev-97f40ef049dded1962bc9e70ad4d197fa8a5cadb.tar.xz linux-dev-97f40ef049dded1962bc9e70ad4d197fa8a5cadb.zip | |
drm/amd/powerplay: Enable UVD powergating for SMU7
This patch enables detecting VCE/UVD PG features and fixes the
UVD powergate function.
Tested on a Tonga (by reading UVD tile/clk bits during playback/idle).
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c index f5a58d489b4b..cf2ee93d8475 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c @@ -149,15 +149,21 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) if (bgate) { cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); + AMD_CG_STATE_UNGATE); + cgs_set_powergating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_GATE); smu7_update_uvd_dpm(hwmgr, true); smu7_powerdown_uvd(hwmgr); } else { smu7_powerup_uvd(hwmgr); - smu7_update_uvd_dpm(hwmgr, false); + cgs_set_powergating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_UVD, + AMD_CG_STATE_UNGATE); cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); + AMD_CG_STATE_GATE); + smu7_update_uvd_dpm(hwmgr, false); } return 0; |