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| author |   Evan Quan <evan.quan@amd.com> | 2018-05-08 18:23:16 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2018-08-27 11:10:29 -0500 |
| commit | b8497699ef8a1858e7246bf1abfa0c84a479f665 (patch) | |
| tree | b9eabfd94eb9676c844906e51689841b56bf4e9a /drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | |
| parent | drm/amd/powerplay: correct force clock level related settings for vega20 (v2) (diff) | |
| download | linux-dev-b8497699ef8a1858e7246bf1abfa0c84a479f665.tar.xz linux-dev-b8497699ef8a1858e7246bf1abfa0c84a479f665.zip | |
drm/amd/powerplay: export vega20 stable pstate clocks
Needed for querying the stable pstate clocks.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c index 289e3ee2006d..7b6e48a01c75 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c @@ -846,6 +846,25 @@ static int vega20_odn_initialize_default_settings( return 0; } +static int vega20_populate_umdpstate_clocks( + struct pp_hwmgr *hwmgr) +{ + struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); + struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table); + struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table); + + hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value; + hwmgr->pstate_mclk = mem_table->dpm_levels[0].value; + + if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL && + mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) { + hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; + hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; + } + + return 0; +} + static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr, PP_Clock *clock, PPCLK_e clock_select) { @@ -992,7 +1011,12 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr) "[EnableDPMTasks] Failed to initialize odn settings!", return result); - return result; + result = vega20_populate_umdpstate_clocks(hwmgr); + PP_ASSERT_WITH_CODE(!result, + "[EnableDPMTasks] Failed to populate umdpstate clocks!", + return result); + + return 0; } static uint32_t vega20_find_lowest_dpm_level( |